What is a storage location in the computers memory called that has a type name and contents?

3.2.5 Memory map

The memory locations in RAM and ROM, which the processor can address, must accommodate space for such requirements as system monitor and utilities, user software and input/output. The manufacturer of the microcomputer assigns an area of memory for each functional requirement and provides the necessary information in a system memory map.

In 8-bit systems, with 64K of addressable memory, the memory map is usually composed of 32K of RAM and 32K of ROM or EPROM. The ROM holds the operating system software and normally some space is available in EPROM form for user firmware. In addition to providing space for user programs, the RAM area contains the system stack and the visual monitor data storage. The I/O facilities are also assigned an area of memory in a memory mapped system.

In a 6502 or 6800 based system the RAM is usually low down in memory and the ROM is high up. A typical memory map is shown in Figure 3.3. The I/O is accommodated anywhere within the above structure and varies from one manufacturer to another.

The display screen RAM is often fitted with a moveable boundary in order to set variable resolution modes for graphics. Typically, the screen memory need only be IK for a text mode to give a 40 × 25 character display. This would be insufficient for computer graphics and a high resolution would require 20K of memory to MAP the screen. It should be noted that this greatly reduces the amount of RAM available to the user.

8080- and Z80-based systems have a distribution of memory similar to that as shown in Figure 3.3. The ROM, however, is usually low down and the RAM high up in the memory map. The 16-bit PCs, with a 20-bit address bus, have 1M byte of addressable memory with the RAM comprising the first three quarters and ROM occupying the last quarter. A general memory map showing the distribution of RAM/ROM for a PC is given in Figure 3.4.

A familiarity with the memory map of the system to be used in any data-acquisition application is essential, since it indicates the areas reserved for the operating system. The programmer can then knowledgeably determine the locations available for data storage and machine-code programs.

Simple Data Accesses

Normally the memory locations (physical addresses) of software variables are defined by the linker. However, we can write the software code to access to the variables as long as we know the symbol of the variables. For example, if we need to calculate the sum of an integer array “DataIn” with 10 elements (32-bit each) and put the result in another variable called “Sum” (also 32-bit), we can use the following assembly code:

LDR    r0,=DataIn; Get the address of variable 'DataIn'

MOVS  r1, #10    ; loop counter

MOVS  r2, #0     ; Result - starting from 0

add_loop

LDM    r0!,{r3}  ; Load result and increment address

ADDS  r2, r3     ; add to result

SUBS  r1, #1     ; increment loop counter

BNE    add_loop

LDR    r0,=Sum   ; Get the address of variable 'Sum'

STR    r2,[r0]    ; Save result to Sum

In the preceding example, we use the LDM instruction rather than a normal LDR instruction. This allows us to read the memory and increment the address to the next array element at the same time.

When using assembly to access data, we need to pay attention to a few things:

Use correct instruction for corresponding data size. Different instructions are available for different data sizes.

Make sure that the access is aligned. If an access is unaligned, it will trigger a fault exception. This can happen if an instruction of incorrect data size is used to access a data.

Various addressing modes are available and can simplify your assembly codes. For example, when programming/accessing a peripheral, you can set a register to its base address value and then use an immediate offset addressing mode for accessing each register. In this way, you do not have to set up the register address every time a different register is accessed.

I.D Special Cycles

Frequently, consecutive memory locations must be transferred over the bus. Moving the address once and incrementing a counter on the memory are more efficient than sending the address each time, especially if the bus is multiplexed. Block transfers are supported by the most complex buses and are available with limitations on the most recent 32-bit microprocessors.

Reading from many devices simultaneously is called broadcall. This costs additional bus lines and transfer time and is not frequently implemented.

Combined cycles are possible. Read–modify–write cycles are interesting in multiprocessor systems. Read-after-write cycles are never implemented because one has confidence in what has been written.

Finally, split cycles are a way of having only write cycles in the system. In order to read some information, one writes a read request and waits. The slave interrupts the master to get its information read, and the process may continue. This is useful when the slave, for example, a disk interface, transfers blocks of data and is slow: It would be inefficient to wait for an acknowledge.

5.2 Memory Maps

The Cortex-M3 processor has a fixed memory map (see Figure 5.1). This makes it easier to port software from one Cortex-M3 product to another. For example, components described in previous sections, such as Nested Vectored Interrupt Controller (NVIC) and Memory Protection Unit (MPU), have the same memory locations in all Cortex-M3 products. Nevertheless, the memory map definition allows great flexibility so that manufacturers can differentiate their Cortex-M3-based product from others.

Some of the memory locations are allocated for private peripherals such as debugging components. They are located in the private peripheral memory region. These debugging components include the following:

Fetch Patch and Breakpoint Unit (FPB)

Data Watchpoint and Trace Unit (DWT)

Instrumentation Trace Macrocell (ITM)

Embedded Trace Macrocell (ETM)

Trace Port Interface Unit (TPIU)

ROM table

The details of these components are discussed in later chapters on debugging features.

The Cortex-M3 processor has a total of 4 GB of address space. Program code can be located in the code region, the Static Random Access Memory (SRAM) region, or the external RAM region. However, it is best to put the program code in the code region because with this arrangement, the instruction fetches and data accesses are carried out simultaneously on two separate bus interfaces.

The SRAM memory range is for connecting internal SRAM. Access to this region is carried out via the system interface bus. In this region, a 32-MB range is defined as a bit-band alias. Within the 32-bit‑band alias memory range, each word address represents a single bit in the 1-MB bit-band region. A data write access to this bit-band alias memory range will be converted to an atomic READ-MODIFY-WRITE operation to the bit-band region so as to allow a program to set or clear individual data bits in the memory. The bit-band operation applies only to data accesses not instruction fetches. By putting Boolean information (single bits) in the bit-band region, we can pack multiple Boolean data in a single word while still allowing them to be accessible individually via bit-band alias, thus saving memory space without the need for handling READ-MODIFY-WRITE in software. More details on bit-band alias can be found later in this chapter.

Another 0.5-GB block of address range is allocated to on-chip peripherals. Similar to the SRAM region, this region supports bit-band alias and is accessed via the system bus interface. However, instruction execution in this region is not allowed. The bit-band support in the peripheral region makes it easy to access or change control and status bits of peripherals, making it easier to program peripheral control.

Two slots of 1-GB memory space are allocated for external RAM and external devices. The difference between the two is that program execution in the external device region is not allowed, and there are some differences with the caching behaviors.

The last 0.5-GB memory is for the system-level components, internal peripheral buses, external peripheral bus, and vendor-specific system peripherals. There are two segments of the private peripheral bus (PPB):

Advanced High-Performance Bus (AHB) PPB, for Cortex-M3 internal AHB peripherals only; this includes NVIC, FPB, DWT, and ITM

Advance Peripheral Bus (APB) PPB, for Cortex-M3 internal APB devices as well as external peripherals (external to the Cortex-M3 processor); the Cortex-M3 allows chip vendors to add additional on-chip APB peripherals on this private peripheral bus via an APB interface

The NVIC is located in a memory region called the system control space (SCS) (see Figure 5.2). Besides providing interrupt control features, this region also provides the control registers for SYSTICK, MPU, and code debugging control.

The remaining unused vendor-specific memory range can be accessed via the system bus interface. However, instruction execution in this region is not allowed.

The Cortex-M3 processor also comes with an optional MPU. Chip manufacturers can decide whether to include the MPU in their products.

What we have shown in the memory map is merely a template; individual semiconductor vendors provide detailed memory maps including the actual location and size of ROM, RAM, and peripheral memory locations.

4.7.12.1 Data transfer

This loads an accumulator from a specified memory location and writes the contents of the accumulator into a specified memory location. Most CPUs have variations such as adding contents of memory location to the accumulator and exchanging the contents of the accumulator and memory locations.

CPUs with multiple registers also have some instructions which can move data to and from these registers, as well as the accumulator. Those with 16-bit or greater word lengths may have versions of these and other instruction types which operate on bytes as well as words.

With a double operand addressing mode (see Section 4.7.8) a generalized ‘Move’ instruction allows the contents of any memory location or register to be transferred to any other memory location or register.

Indirect

Indirect addressing is where the memory location of the address is stored in the location specified by the instruction. This is one step removed from direct addressing. Indirect addressing is where the memory location’s address, not value, is then specified by the instruction’s operand. This is referred to as one level of indirection. If the location of the address is further contained in the memory location’s address, then this is considered two levels of indirection. In theory, this can be continued indefinitely.

For example, from page 19 in the data sheet, the code first initializes the pointer to 0x10.

  MOVLW  0x10

  MOVWF  FSR

Then, the INDF is cleared and the pointer is incremented for the next instruction in a loop.

  CLRF INDF

  INCF FSR,F

2.1.6 Signed numbers

An 8-bit memory location can cover the range of decimal integers from 0 to 255. To enable an 8-bit memory location to hold both positive and negative numbers, the most significant bit (msb) is reserved and is called the sign bit. A sign bit = 1 indicates a negative number. A sign bit = 0 indicates a positive number. The other 7-bit positions are used to represent the magnitude of the number – but the way of doing this is different for positive and negative numbers.

Whether or not a particular binary bit pattern represents a signed or unsigned number depends on the context in which it is being used. For binary numbers starting with 0, there is no confusion since they have the same value whether they are signed or unsigned numbers. For numbers starting with 1, they may be interpreted as an unsigned integer or the 2's complement representation of a negative number.

For signed number representation, the range that can be covered by 8 bits is −128 to +127. Signed positive binary numbers roll over to represent negative numbers after +127.

The +1 step in finding the 2's complement takes into account ±0 possibilities (i.e. 1's complement goes from −127 to −0, and +0 to +127).

Addressing Peripherals

The reason for distinguishing between memory locations and peripherals is that they perform different functions. Memory is a data storage device, while peripherals are input/output devices. However, many microcomputers address memory and peripherals in the same way because they use a design called memory-mapped I/O (input/output). With this design, peripherals, such as data terminals, are equivalent to memory to the CPU so that sending data to a peripheral is as simple as writing data to a memory location. In systems where this type of microcomputer has replaced some digital logic, the digital inputs enter the computer through a designated memory slot. If outputs are required, they exit the computer through another designated memory slot.

The relatively efficient means of input/output of data via memory map facilitates operations such as digital filtering of sampled analog signals or for control operations as explained in Appendix B. In such cases, the A/D converter providing the sampled input would have a specific memory location. Similarly, any D/A or ZOH (see Chapter 2) would also have a designated memory location. Such memory-mapped I/O is particularly helpful for speeding computer operations in discrete time control for automotive systems.

Elementary Programs

The indirect and the indirect autoincrement addressing modes

For the source operand, there are additional addressing modes. The more common of these is the Indirect Addressing Mode, an example of which is:

 mov   @R6,R8

which moves the contents of the memory location pointed to by R6 into R8. But doesn’t the Indexed Mode do the same thing when used with a zero offset? Well, yes. In fact, the ADD example given a little earlier could be rewritten as:

 add   @R8,2(R8).

Not only can you use this last statement in place of the earlier ADD syntax, but the Assembler will actually substitute this Indirect Addressing Mode for the earlier Indexed Addressing Mode, should you write your program using the Indexed Addressing Mode for the source operand. The reason for this is that, although they produce equivalent results, the Indirect Addressing Mode is more compact, requiring just one word of instruction, instead of the three words that the Indexed Addressing Mode requires.

The Indirect Autoincrement Addressing Mode is exactly like the Indirect Addressing Mode, except that it increments the pointing register by 1 or 2 (depending on whether the instruction is for byte-long data or word-long data). This can be useful when loading data from a table (that is, a list of bytes or words in memory). The program can execute a MOV instruction that loads the byte or word from memory and, without using an extra instruction to increment the table pointer, be ready to load the next memory location.